This is formal specification of the RISC-V architecture, written in Sail.

The model specifies assembly language formats of the instructions, the corresponding encoders and decoders, and the instruction semantics. A reading guide to the model is provided in the doc/ subdirectory, along with a guide on how to add a new extension to the model.

The highlight of this release is substantially improved performance on Linux boot after a fix to the handling of superpages in the TLB.

This release adds 13 new extensions; all mandatory extensions for RVAU23 are now supported.

Several configuration parameters have been added, along with new command line options. The model implements a simple external interrupt generator, and the wait duration of instructions like WFI can be specified. The handling of misaligned accesses can bespecified at a more granular level.