Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX (www.phoronix.com)

submitted 2 days ago by JRepin@lemmy.ml to c/riscv@lemmy.ml

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One of the RISC-V SoCs we have been most looking forward to this year is the SpacemiT K3 that features the X100 RISC-V cores that are RVA23 compliant and among the first readily available RVA23 RISC-V platform for running on the likes of Ubuntu 26.04 LTS. In this article is a preview of some very early benchmarks of the SpacemiT K3 with the new Pico-ITX single board computer offering.

The SpacemiT K3 features eight X100 RISC-V cores as well as eight ultra-wide parallel AI computing A100 cores. The X100 cores clock up to 2.4GHz and are RVA23 profile compliant and largely associated as delivering similar performance to the Arm Cortex-A76 cores. The A100 AI cores support INT4 / INT8 / FP8 / FP16 / BF16 and rated for around 60 TOPS API performance. The A100 cores are also among the few RISC-V cores so far available that support RVV 1.0 vector processing.

The SpacemiT K3 Pico-ITX is an interesting little board that pairs the K3 SoC with 10Gb networking, UFS storage, dual M.2 expansion slots, USB Type-C with power delivery and 4K DisplayPort output, and dual channel LPDDR5-6400 memory with 16GB and 32GB configurations offered.

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[-] JRepin@lemmy.ml 2 points 2 days ago* (last edited 2 days ago)

As far as I found out about this until now is that the X100 (normal cores) and A100 (AI core) are almost the same RISC-V cores, mainly only different in th RVV vector registers length spec VLEN (256 vs. 1024). The RISC-V Unprivileged specification in chapter 31.1.2. Implementation-defined Constant Parameters says this about cores with different VLENs:

The vector extension supports writing binary code that under certain constraints will execute portably on harts with different values for the VLEN parameter, provided the harts support the required element types and instructions.

NOTE: Code can be written that will expose differences in implementation parameters.

NOTE: In general, thread contexts with active vector state cannot be migrated during execution between harts that have any difference in VLEN or ELEN parameters.

So regarding this there may not be so much of a problem.

Another probably bigger problem is that the A100 cores are not really RVA23 compliant, since they do not support Hypervisor Extension: RVH 1.0 which is required by RVA23 and is only supported on normal X100 cores. But then again usual user-level code does not use the H extension instructions. So maybe even this might not be such a problem for most user-space code.

Anyways as things currently stand : the code only gets executed automaticaly and scheduled onto 8 X100 cores, A100 cores are ignored, even if it could also run on A100. If you are sure the code can run on A100, you must manualy move/execute them on A100 (and again they are confined to only the A100 cores).

Probably the Linux kernel and scheduling needs to get some upgraded logic to make it able to freeely move code among X100 and A100 in the future. And again it depends on how VLEN is treated, is it fixed in the code or can it dynamically acommodate depending on the core it is currently on.

Oh and A100 cores have support for vendor-specific SpacemiT IME (Integrated Matrix Extension) , which is based on some proposals for future RISC-V extension, but yeah nothing official yet. And looks like these are not supported on X100.

As for SIMD. RISC-V does not have anything official yet, since the normal and more general V vector extension should be used in most (if not all common) cases to replace the SIMD instructions. There are some good cases for SIMD way of ding things but yeah RISC-V has nothing official yet, they are working on a P Packed-SIMD extension that may be available sometime in the future. As far as I could see neither X100 nor A100 support any of these P instructions.

this post was submitted on 20 May 2026

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