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Why does this diagram on CMOS switching show the ground voltage rising?
(programming.dev)
This is from a section on why decoupling capacitors should be attached to CMOS chips. It shows current spikes during transitions. Which then because of the inductance of traces connecting power to the chip, will cause the power rail voltage to droop.
But why is the ground voltage also shown to rise? What does it even mean for ground voltage to rise when ground is what voltage is measured against?
So ground on any implemented circuit is not constant and will have some variation physically where you probe. The schematic abstraction assumes every node is connected with zero ohm, zero length connections but this is of course not the case.
I think what this is showing is that the ground node for this device is noisy and will fluctuate as it is trying to deal with the current spikes. It’s probably relative to the expected ground.
I’ve not ever seen this drawn like this before, but have read about the phenomenon in a few different texts.